1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to an input circuit having signature circuits arranged in parallel in a semiconductor device.
2. Description of the Related Art
Signature circuits are used for various purposes, for example, for marking defective products during a packaging process and for identifying products to avoid various products from being confused with each other.
In semiconductor products which interface at low frequencies, the low frequency characteristics of an input/output port are rarely considered. However, recently developed semiconductor products operate at high frequencies or speed. One skilled in the art can appreciate that high speed electronic interfacing exhibits different and often distorting characteristics. Accordingly, it is necessary that the semiconductor products operating at high speed are equipped with input/output ports that can handle operation in high frequency interfacing correctly, for example, at several hundred MHZ. One problem in high speed operation is the varying impedance of an input/output of a semiconductor-product in high speed interfacing. Various technical approaches have been proposed to reduce the problems associated with the impedance of an input/output port of a semiconductor product.
The impedance characteristics of an input port depends on the resistance of internal signal lines connected to the input port, inductance, parasitic capacitance and the capacitance of an input buffer. Moreover, circuits (such as static electricity dischargers, waveform clamping circuits and connection test diodes) connected to or accompanied with the input port and parasitic capacitance of a signature circuit for indexing a semiconductor product affects the impedance characteristics of the input port, typically by increasing its resistance.
FIG. 1 is a diagram illustrating a conventional input circuit. In the conventional input circuit, first, second and n-th signature circuits 110, 112 and 114 are provided for respective input buffers 100,102 and 104 to obtain a large number of indexes. Each of the signature circuits 110,112 and 114 includes fuses (e.g., F20 in FIG. 2), and whether the fuses are cut or not determines whether current flows in each of the signature circuits 110,112 and 114.
FIG. 2 is a diagram illustrating an individual signature circuit of the input circuit of FIG. 1. The individual signature circuit includes a master fuse F20 and NMOS transistors MN21, MN22 and MN23. Each of the NMOS transistors MN21, MN22 and MN23 has a gate and a source, which are connected to each other, and operates as a diode. The NMOS transistors MN21, MN22 and MN23 are connected in series. A waveform clamping circuit 208 is provided between an input port INPUT1 and an input buffer 200 to compensate for waveform of an input signal applied to the input buffer 200.
Information stored in the individual signature circuit 110 is obtained by detecting a voltage of the input port at which current flows in the individual signature circuit while varying the voltage of the input port. If the master fuse F20 is not cut, current flows in the signature circuit 110 when the voltage of the input port is higher than a power supply voltage VDD by the sum of the threshold voltages of the NMOS transistors MN21, MN22 and MN23. Various kinds of information on a packaged semiconductor device are represented by a combination of fuses of signature circuits which are cut or uncut.
The impedance of an input/output port having the individual signature circuit 110 includes parasitic capacitance such as gate overlap capacitance and junction capacitance of the NMOS transistor MN23. The parasitic capacitance of the individual signature circuit 110 causes parasitic effects when the associated input port is interfaced at high speed.
Consequently, signature circuits are typically used with input/output ports interfacing at low speed. Accordingly, conventional input circuits in a semiconductor device having signature circuits have limited number of available indexes due to high impedance at high speed interfacing.
Moreover, a conventional individual signature circuit cannot be used together with the waveform clamping circuit 208. The waveform clamping circuit 208 is used for compensating for the waveform of an input signal within a predetermined range and is normally applied to an input device in a semiconductor device. Usual waveform clamping circuits clamp a signal of a voltage higher than an external power supply voltage VDD by 1 VT (VT is the threshold voltage of a transistor in a waveform clamping circuit) and a signal of a voltage lower than an external ground voltage VSS by 1 VT. For example, when a voltage higher than the external power supply voltage VDD by 1 VT is applied to the input port INPUT1, a transistor of the waveform clamping circuit 208 is turned on, and current is diverted to the waveform clamping circuit. Consequently, the current flowing in the individual signature circuit 110 cannot be detected.
Therefore, a need exists for a signature circuit which can decrease the impedance of an input/output port and can be used together with a waveform clamping circuit in a semiconductor device.
To solve the above problems, it is an object of the present invention to provide an input circuit in a semiconductor device for obtaining a large number of indexes and capable of interfacing at high frequency.
It is another object of the present invention to provide a signature circuit which can be used together with a waveform clamping circuit provided for an input port in a semiconductor device.
Accordingly, to achieve the above and other objects of the invention, there is provided an individual signature circuit in a semiconductor device having an input line for propagating a signal applied from an input port to an input buffer. Two or more individual signature circuits are connected in parallel between the input line and a predetermined voltage node and selectively enabled in response to a predetermined control signal. An individual signature circuit includes an indexer and a selector connected in series between the voltage node and the input line.
Preferably, two terminals of the selector are electrically short-circuited or snapped in response to the control signal, and the indexer includes one or more voltage reducing devices connected in series between input and output terminals of the indexer and signature fuses each of which is connected in parallel to corresponding one of the voltage reducing devices. Therefore, voltage drop in the indexer varies with a combination of the signature fuses which are cut or uncut.
Preferably, the indexer may include one or more variable resistors connected in series between input and output terminals of the indexer and signature fuses each of which is connected in parallel to corresponding one of the variable resistors. Therefore, amount of current flowing between the input and output terminals of the indexer varies with a combination of the signature fuses which are cut or uncut.
Preferably, the indexer may include one or more variable resistors connected in parallel between input and output terminals of the indexer and signature fuses each of which is connected in series to corresponding one of the variable resistors. Therefore, amount of current flowing between the input and output terminals of the indexer varies with a combination of the signature fuses which are cut or uncut.
Preferably, the indexer may include one or more voltage reducing devices connected in series between input and output terminals of the indexer and signature fuses each of which is connected in parallel to a different number of voltage reducing devices. Therefore, a voltage drop across the indexer determined by the different number of voltage reducing devices varies with a combination of the signature fuses which are cut or uncut.
By using an input circuit having one or more individual signature circuits according to the present invention, various kinds of information on a semiconductor device operating at high speed can be indexed. In addition, an individual signature circuit of the present invention can be used together with a waveform clamping circuit provided at an input port of a semiconductor device.